verilator: fix typo (#9559)

pages/common/verilator.md

@@ -1,6 +1,6 @@
 # verilator
 
-> Converts Verilog and SystemVerilog hardware description language (HDL) designs into a C++ or SystemC model that after compiling can be executed.
+> Converts Verilog and SystemVerilog hardware description language (HDL) design into a C++ or SystemC model to be executed after compiling.
 > More information: <https://veripool.org/guide/latest/>.
 
 - Build a specific C project in the current directory: